EFFECTS OF MULTI-LEVEL CACHE ORGANIZATION AND INTERCONNECT NETWORK ON PERFORMANCE OF MULTI-CORE CHIP

Abstract

Today, chip ASIC, PLD and FPGA technology has created opportunities for researchers to design and manufacture processor chips. Meanwhile, the multi-core chip technology with a multi-level cache organization and a choice of network configuration connecting cores to ensure high performance for multi-core chip applications in the speed parallel computing systems is a trend of researching and manufacturing today. The article stated that one of the concerns in the multi-core chip technology is cache organization, core interconnect networks on chip, and offering calculations for performance evaluation of multi-level cache organization through determining acceleration rate achieving, and proposes solutions to determine communication overhead of a core processor interconnect network - a factor that affects the execution speed of parallel computing of multi-core chip.